The present invention relates to a method of manufacturing semiconductor devices having high reliability. The present invention has particular applicability in manufacturing high density, multi-level flash-memory semiconductor devices with feature dimensions in the deep sub-micron regime.
As integrated circuit geometries continue to plunge into the deep sub-micron regime the requirements for dimensional accuracy become increasingly difficult to satisfy. Integration technology is considered one of the most demanding aspects of fabricating ULSI devices. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing flash memory semiconductor devices having a design rule about 0.18 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive level comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. Excess conductive material or the overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with an upper conductive line.
As device geometries proceed into the deep submicron regime, the formation of reliable contacts and vias becomes particularly problematic. For example, as the contact and via openings are reduced in diameter and aspect ratios increased, the openings become more vulnerable to defects, such as particulate contamination which clog the openings preventing complete filling and, hence, adversely impacting interconnect reliability.
Accordingly, there exists a need for methodology enabling the manufacture of semiconductor devices with improved reliability, including semiconductor devices containing typical MOS transistors as well as flash memory devices, such as electrically erasable programmable read only memory (EEPROM) devices. There exists a particular need for methodology enabling the manufacture of semiconductor devices having features in the deep sub-micron range and containing reliable vias and contacts.
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability.
Another advantage of the present invention is a method of manufacturing a semiconductor device having features in the deep sub-micron regime with highly reliable vias and contacts.
A further advantage of the present invention is a method of manufacturing flash memory semiconductor devices having features in the deep sub-micron regime with highly reliable vias and contacts.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising depositing a layer of silicon oxynitride, over a substrate, by the following sequential steps: (a): flowing silane (SiH4), nitrous oxide (N2O) and nitrogen (N2); (b): initiating deposition of silicon oxynitride at a first power while flowing SiH4, N2O and N2; (c): ramping down by reducing the power, discontinuing the flow of SiH4 and continuing the flow of N2O and N2; and (d): discontinuing the power and flow of N2O and N2.
Embodiments of the present invention include conducting the step (c) into stages: (c1) ramping down by reducing the first power to a second power, discontinuing the flow of SiH4 and continuing the flow of N2O and N2; and (c2) continuing ramping down by reducing the second power to a third power and continuing the flow of N2O and N2. Further embodiments of the present invention including depositing the silicon oxynitride at a first RF power of about 290 to about 360 watts; ramping down to a second RF power of about 170 to about 210 watts and continuing to ramp down to a third RF power of about 80 watts to about 100 watts before pumping down. Further embodiments of the present invention comprise depositing the silicon oxynitride layer as an anti-reflective coating (ARC) at a thickness of about 260xc3x85 to about 340xc3x85, overlying a flash memory cell, and forming a contact hole through the silicon oxynitride ARC to a source/drain region of the flash memory cell.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present invention are described simply by way of illustrated of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.